Messages in this thread | | | Subject | Re: [PATCH v2] spi: bcm2835: Enable shared interrupt support | From | Nicolas Saenz Julienne <> | Date | Fri, 05 Jun 2020 12:58:01 +0200 |
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On Fri, 2020-06-05 at 10:46 +0200, Nicolas Saenz Julienne wrote: > Hi Florian, > Thanks for taking over this! > > On Thu, 2020-06-04 at 14:28 -0700, Florian Fainelli wrote: > > The 4 SPI controller instances added in BCM2711 and BCM7211 SoCs (SPI3, > > SPI4, SPI5 and SPI6) share the same interrupt line with SPI0. > > I think this isn't 100% correct. SPI0 has its own interrupt, but SPI[3-6] > share > the same interrupt.
I'm wrong here, I missed this in bcm2711.dtsi:
&spi { interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; };
Sorry for the noise.
Regards, Nicolas
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