Messages in this thread | | | Date | Mon, 29 Jun 2020 16:43:25 +0200 | From | Johan Hovold <> | Subject | Re: [PATCH 4/5] mfd: sprd-sc27xx-spi: Fix divide by zero when allocating register offset/mask |
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On Mon, Jun 29, 2020 at 10:35:06PM +0800, Baolin Wang wrote: > On Mon, Jun 29, 2020 at 10:01 PM Lee Jones <lee.jones@linaro.org> wrote: > > > > On Mon, 29 Jun 2020, Johan Hovold wrote: > > > > > On Mon, Jun 29, 2020 at 01:32:14PM +0100, Lee Jones wrote: > > > > Since ddata->irqs[] is already zeroed when allocated by devm_kcalloc() and > > > > dividing 0 by anything is still 0, there is no need to re-assign > > > > ddata->irqs[i].* values. Instead, it should be safe to begin at 1. > > > > > > > > This fixes the following W=1 warning: > > > > > > > > drivers/mfd/sprd-sc27xx-spi.c:255 sprd_pmic_probe() debug: sval_binop_unsigned: divide by zero > > > > > > > > Cc: Orson Zhai <orsonzhai@gmail.com> > > > > Cc: Baolin Wang <baolin.wang7@gmail.com> > > > > Cc: Chunyan Zhang <zhang.lyra@gmail.com> > > > > Signed-off-by: Lee Jones <lee.jones@linaro.org> > > > > --- > > > > drivers/mfd/sprd-sc27xx-spi.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c > > > > index c305e941e435c..694a7d429ccff 100644 > > > > --- a/drivers/mfd/sprd-sc27xx-spi.c > > > > +++ b/drivers/mfd/sprd-sc27xx-spi.c > > > > @@ -251,7 +251,7 @@ static int sprd_pmic_probe(struct spi_device *spi) > > > > return -ENOMEM; > > > > > > > > ddata->irq_chip.irqs = ddata->irqs; > > > > - for (i = 0; i < pdata->num_irqs; i++) { > > > > + for (i = 1; i < pdata->num_irqs; i++) { > > > > ddata->irqs[i].reg_offset = i / pdata->num_irqs; > > > > ddata->irqs[i].mask = BIT(i % pdata->num_irqs); > > > > } > > > > > > This doesn't look right either. > > > > > > First, the loop is never executed if num_irqs is zero. > > > > The point of the patch is that 0 entries are never processed.
So what's the problem? There's no division by zero here.
And what compiler are you using, Lee? Seems broken.
> > > Second, the current code looks bogus too as reg_offset is always set to > > > zero and mask to BIT(i)... > > Now the result is correct, since all PMIC irq mask bits are in one > register now, which means the reg_offset is always 0 can work well. > But I think the logics still can be improved if our PMIC irq numbers > are larger than 32 in future.
The code is still bogus as pointed out above. Why do you bother to divide by num_irqs at all?
And what have you guys been smoking? ;)
Johan
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