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    Subject[PATCH v2 01/13] clk: qcom: gcc: fix sm8150 GPU and NPU clocks
    Date
    Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
    should be a 500us delay and not skip, however this matches what was done
    for other clocks that had 500us delay in downstream.

    Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")

    Signed-off-by: Jonathan Marek <jonathan@marek.ca>
    ---
    drivers/clk/qcom/gcc-sm8150.c | 8 ++++++--
    1 file changed, 6 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
    index 72524cf11048..55e9d6d75a0c 100644
    --- a/drivers/clk/qcom/gcc-sm8150.c
    +++ b/drivers/clk/qcom/gcc-sm8150.c
    @@ -1617,6 +1617,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
    };

    static struct clk_branch gcc_gpu_gpll0_clk_src = {
    + .halt_check = BRANCH_HALT_SKIP,
    .clkr = {
    .enable_reg = 0x52004,
    .enable_mask = BIT(15),
    @@ -1632,13 +1633,14 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
    };

    static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
    + .halt_check = BRANCH_HALT_SKIP,
    .clkr = {
    .enable_reg = 0x52004,
    .enable_mask = BIT(16),
    .hw.init = &(struct clk_init_data){
    .name = "gcc_gpu_gpll0_div_clk_src",
    .parent_hws = (const struct clk_hw *[]){
    - &gcc_gpu_gpll0_clk_src.clkr.hw },
    + &gpll0_out_even.clkr.hw },
    .num_parents = 1,
    .flags = CLK_SET_RATE_PARENT,
    .ops = &clk_branch2_ops,
    @@ -1729,6 +1731,7 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
    };

    static struct clk_branch gcc_npu_gpll0_clk_src = {
    + .halt_check = BRANCH_HALT_SKIP,
    .clkr = {
    .enable_reg = 0x52004,
    .enable_mask = BIT(18),
    @@ -1744,13 +1747,14 @@ static struct clk_branch gcc_npu_gpll0_clk_src = {
    };

    static struct clk_branch gcc_npu_gpll0_div_clk_src = {
    + .halt_check = BRANCH_HALT_SKIP,
    .clkr = {
    .enable_reg = 0x52004,
    .enable_mask = BIT(19),
    .hw.init = &(struct clk_init_data){
    .name = "gcc_npu_gpll0_div_clk_src",
    .parent_hws = (const struct clk_hw *[]){
    - &gcc_npu_gpll0_clk_src.clkr.hw },
    + &gpll0_out_even.clkr.hw },
    .num_parents = 1,
    .flags = CLK_SET_RATE_PARENT,
    .ops = &clk_branch2_ops,
    --
    2.26.1
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