Messages in this thread | | | From | Zong Li <> | Date | Mon, 29 Jun 2020 13:52:15 +0800 | Subject | Re: [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V |
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On Mon, Jun 29, 2020 at 12:53 PM Anup Patel <anup@brainfault.org> wrote: > > On Mon, Jun 29, 2020 at 8:49 AM Zong Li <zong.li@sifive.com> wrote: > > > > This patch set adds raw event support on RISC-V. In addition, we > > introduce the DT mechanism to make our perf more generic and common. > > > > Currently, we set the hardware events by writing the mhpmeventN CSRs, it > > would raise an illegal instruction exception and trap into m-mode to > > emulate event selector CSRs access. It doesn't make sense because we > > shouldn't write the m-mode CSRs in s-mode. Ideally, we should set event > > selector through standard SBI call or the shadow CSRs of s-mode. We have > > prepared a proposal of a new SBI extension, called "PMU SBI extension", > > but we also discussing the feasibility of accessing these PMU CSRs on > > s-mode at the same time, such as delegation mechanism, so I was > > wondering if we could use SBI calls first and make the PMU SBI extension > > as legacy when s-mode access mechanism is accepted by Foundation? or > > keep the current situation to see what would happen in the future. > > > > This patch set also introduces the DT mechanism, we don't want to add too > > much platform-dependency code in perf like other architectures, so we > > put the mapping of generic hardware events to DT, then we can easy to > > transfer generic hardware events to vendor's own hardware events without > > any platfrom-dependency stuff in our perf. > > Please re-write this series to have RISC-V PMU driver as a regular > platform driver as drivers/perf/riscv_pmu.c. > > The PMU related sources will have to be removed from arch/riscv. > > Based on implementation of final drivers/perf/riscv_pmu.c we will > come-up with drivers/perf/riscv_sbi_pmu.c driver for SBI perf counters. >
There are some different ways to implement perf, and current implementation seems to be consensus when perf was introduced at the beginning [0][1]. I don't persist to which one, I could change the implementation as you mentioned if it is a new consensus one.
[0] https://github.com/riscv/riscv-linux/pull/124#issuecomment-367563910 [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/f19TmCNP6yA
> Regards, > Anup > > > > > Zong Li (6): > > dt-bindings: riscv: Add YAML documentation for PMU > > riscv: dts: sifive: Add DT support for PMU > > riscv: add definition of hpmcounter CSRs > > riscv: perf: Add raw event support > > riscv: perf: introduce DT mechanism > > riscv: remove PMU menu of Kconfig > > > > .../devicetree/bindings/riscv/pmu.yaml | 59 +++ > > arch/riscv/Kconfig | 13 - > > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 13 + > > arch/riscv/include/asm/csr.h | 58 +++ > > arch/riscv/include/asm/perf_event.h | 100 ++-- > > arch/riscv/kernel/Makefile | 2 +- > > arch/riscv/kernel/perf_event.c | 471 +++++++++++------- > > 7 files changed, 471 insertions(+), 245 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml > > > > -- > > 2.27.0 > >
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