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    Subject[PATCH 4.19 108/131] KVM: X86: Fix MSR range of APIC registers in X2APIC mode
    Date
    From: Xiaoyao Li <xiaoyao.li@intel.com>

    commit bf10bd0be53282183f374af23577b18b5fbf7801 upstream.

    Only MSR address range 0x800 through 0x8ff is architecturally reserved
    and dedicated for accessing APIC registers in x2APIC mode.

    Fixes: 0105d1a52640 ("KVM: x2apic interface to lapic")
    Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
    Message-Id: <20200616073307.16440-1-xiaoyao.li@intel.com>
    Cc: stable@vger.kernel.org
    Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
    Reviewed-by: Jim Mattson <jmattson@google.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/kvm/x86.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
    index 50d59ad34619c..0aa5c4134b90e 100644
    --- a/arch/x86/kvm/x86.c
    +++ b/arch/x86/kvm/x86.c
    @@ -2499,7 +2499,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    return kvm_mtrr_set_msr(vcpu, msr, data);
    case MSR_IA32_APICBASE:
    return kvm_set_apic_base(vcpu, msr_info);
    - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
    + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
    return kvm_x2apic_msr_write(vcpu, msr, data);
    case MSR_IA32_TSCDEADLINE:
    kvm_set_lapic_tscdeadline_msr(vcpu, data);
    @@ -2797,7 +2797,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    case MSR_IA32_APICBASE:
    msr_info->data = kvm_get_apic_base(vcpu);
    break;
    - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
    + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
    return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
    break;
    case MSR_IA32_TSCDEADLINE:
    --
    2.25.1
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