Messages in this thread | | | From | Andy Duan <> | Subject | RE: [EXT] [PATCH v4 2/2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible | Date | Sun, 28 Jun 2020 05:05:15 +0000 |
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From: Sven Van Asbroeck <thesven73@gmail.com> Sent: Thursday, June 25, 2020 10:01 PM > On imx6, the ethernet reference clock (clk_enet_ref) can be generated by > either the imx6, or an external source (e.g. an oscillator or the PHY). When > generated by the imx6, the clock source (from ANATOP) must be routed to the > input of clk_enet_ref via two pads on the SoC, typically via a dedicated track > on the PCB. > > On an imx6 plus however, there is a new setting which enables this clock to > be routed internally on the SoC, from its ANATOP clock source, straight to > clk_enet_ref, without having to go through the SoC pads. > > Board designs where the clock is generated by the imx6 should not be > affected by routing the clock internally. Therefore on a plus, we can enable > internal routing by default. > > Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
For the version:
Reviewed-by: Fugang Duan <fugang.duan@nxp.com> > --- > v3 -> v4: > - avoid double-check for IS_ERR(gpr) by including Fabio Estevam's > patch. > v2 -> v3: > - remove check for imx6q, which is already implied when > of_machine_is_compatible("fsl,imx6qp") > v1 -> v2: > - Fabio Estevam: use of_machine_is_compatible() to determine if we > are running on an imx6 plus. > > To: Shawn Guo <shawnguo@kernel.org> > To: Andy Duan <fugang.duan@nxp.com> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > arch/arm/mach-imx/mach-imx6q.c | 14 ++++++++++++++ > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + > 2 files changed, 15 insertions(+) > > diff --git a/arch/arm/mach-imx/mach-imx6q.c > b/arch/arm/mach-imx/mach-imx6q.c index ae89ad93ca83..07cfe0d349c3 > 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -204,6 +204,20 @@ static void __init imx6q_1588_init(void) > regmap_update_bits(gpr, IOMUXC_GPR1, > IMX6Q_GPR1_ENET_CLK_SEL_MASK, > clksel); > > + /* > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally > routed to > + * be the PTP clock source, instead of having to be routed through > + * pads. > + * Board designs which route the ANATOP/CCM clock through pads > are > + * unaffected when routing happens internally. So on these designs, > + * route internally by default. > + */ > + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && > + of_machine_is_compatible("fsl,imx6qp")) > + regmap_update_bits(gpr, IOMUXC_GPR5, > + IMX6Q_GPR5_ENET_TXCLK_SEL, > + IMX6Q_GPR5_ENET_TXCLK_SEL); > + > clk_put(enet_ref); > put_ptp_clk: > clk_put(ptp_clk); > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > index d4b5e527a7a3..eb65d48da0df 100644 > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > @@ -240,6 +240,7 @@ > #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) > > #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) > +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) > #define IMX6Q_GPR5_SATA_SW_PD BIT(10) > #define IMX6Q_GPR5_SATA_SW_RST BIT(11) > > -- > 2.17.1
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