Messages in this thread | | | Subject | Re: [PATCH 1/7] iommu/vt-d: Enforce PASID devTLB field mask | From | Lu Baolu <> | Date | Thu, 25 Jun 2020 15:14:45 +0800 |
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On 2020/6/23 23:43, Jacob Pan wrote: > From: Liu Yi L <yi.l.liu@intel.com> > > Set proper masks to avoid invalid input spillover to reserved bits. >
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards, baolu
> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> > --- > include/linux/intel-iommu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index 4100bd224f5c..729386ca8122 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -380,8 +380,8 @@ enum { > > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > -#define QI_DEV_EIOTLB_GLOB(g) ((u64)g) > -#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) > +#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1) > +#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) > #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) > #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) > #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ >
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