Messages in this thread | | | From | Jerome Brunet <> | Subject | Re: [PATCH] clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 | Date | Thu, 25 Jun 2020 08:30:45 +0200 |
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On Sat 20 Jun 2020 at 18:14, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't > know the relation between this clock and RGMII Ethernet. It turns out > that fclk_div2 is used as "timing adjustment clock" to generate the RX > delay on the MAC side - which was enabled by u-boot on Odriod-C1. When > using the RX delay on the PHY side or not using a RX delay at all then > this clock can be disabled. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Applied. Thx
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