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    Subject[PATCH 5.7 218/477] PCI: aardvark: Train link immediately after enabling training
    Date
    From: Pali Rohár <pali@kernel.org>

    [ Upstream commit 6964494582f56a3882c2c53b0edbfe99eb32b2e1 ]

    Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link
    training and starting link training causes detection issues with some
    buggy cards (such as Compex WLE900VX).

    Move the code which enables link training immediately before the one
    which starts link traning.

    This fixes detection issues of Compex WLE900VX card on Turris MOX after
    cold boot.

    Link: https://lore.kernel.org/r/20200430080625.26070-2-pali@kernel.org
    Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready...")
    Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
    Signed-off-by: Pali Rohár <pali@kernel.org>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Rob Herring <robh@kernel.org>
    Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pci/controller/pci-aardvark.c | 15 +++++++++------
    1 file changed, 9 insertions(+), 6 deletions(-)

    diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
    index 3a6d07dc0a385..74b90940a9d46 100644
    --- a/drivers/pci/controller/pci-aardvark.c
    +++ b/drivers/pci/controller/pci-aardvark.c
    @@ -300,11 +300,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
    reg |= LANE_COUNT_1;
    advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);

    - /* Enable link training */
    - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
    - reg |= LINK_TRAINING_EN;
    - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
    -
    /* Enable MSI */
    reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
    reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
    @@ -346,7 +341,15 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
    */
    msleep(PCI_PM_D3COLD_WAIT);

    - /* Start link training */
    + /* Enable link training */
    + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
    + reg |= LINK_TRAINING_EN;
    + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
    +
    + /*
    + * Start link training immediately after enabling it.
    + * This solves problems for some buggy cards.
    + */
    reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
    reg |= PCIE_CORE_LINK_TRAINING;
    advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
    --
    2.25.1


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