lkml.org 
[lkml]   [2020]   [Jun]   [19]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.4 015/261] spi: pxa2xx: Apply CS clk quirk to BXT
    Date
    From: Evan Green <evgreen@chromium.org>

    [ Upstream commit 6eefaee4f2d366a389da0eb95e524ba82bf358c4 ]

    With a couple allies at Intel, and much badgering, I got confirmation
    from Intel that at least BXT suffers from the same SPI chip-select
    issue as Cannonlake (and beyond). The issue being that after going
    through runtime suspend/resume, toggling the chip-select line without
    also sending data does nothing.

    Add the quirk to BXT to briefly toggle dynamic clock gating off and
    on, forcing the fabric to wake up enough to notice the CS register
    change.

    Signed-off-by: Evan Green <evgreen@chromium.org>
    Cc: Shobhit Srivastava <shobhit.srivastava@intel.com>
    Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/spi/spi-pxa2xx.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
    index d0d6f1bda1b6..7f4285e2ae68 100644
    --- a/drivers/spi/spi-pxa2xx.c
    +++ b/drivers/spi/spi-pxa2xx.c
    @@ -148,6 +148,7 @@ static const struct lpss_config lpss_platforms[] = {
    .tx_threshold_hi = 48,
    .cs_sel_shift = 8,
    .cs_sel_mask = 3 << 8,
    + .cs_clk_stays_gated = true,
    },
    { /* LPSS_CNL_SSP */
    .offset = 0x200,
    --
    2.25.1


    \
     
     \ /
      Last update: 2020-06-19 18:12    [W:4.589 / U:0.004 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site