Messages in this thread Patch in this message | | | From | Hanks Chen <> | Subject | [PATCH v6 6/7] clk: mediatek: add UART0 clock support | Date | Thu, 18 Jun 2020 19:33:37 +0800 |
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Add MT6779 UART0 clock support.
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Signed-off-by: mtk01761 <wendell.lin@mediatek.com> --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", -- 1.7.9.5 | |