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    Subject[PATCH AUTOSEL 5.7 151/388] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
    Date
    From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

    [ Upstream commit da1978ac3d6cf278dedf5edbf350445a0fff2f08 ]

    Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not
    easy to see that the vendor kernel does the same, but it actually does.
    meson_clk_pll_ops in mainline still cannot fully recalculate all rates
    from the HDMI PLL registers because some register bits (at the time of
    writing it's unknown which bits are used for this) double the HDMI PLL
    output rate (compared to simply considering M, N and FRAC) for some (but
    not all) PLL settings.

    Update the vid_pll_in_sel parent so our clock calculation works for
    simple clock settings like the CVBS output (where no rate doubling is
    going on). The PLL ops need to be fixed later on for more complex clock
    settings (all HDMI rates).

    Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees")
    Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
    Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
    Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
    Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/meson/meson8b.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
    index 34a70c4b4899..ac4a883acd2a 100644
    --- a/drivers/clk/meson/meson8b.c
    +++ b/drivers/clk/meson/meson8b.c
    @@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
    * Meson8m2: vid2_pll
    */
    .parent_hws = (const struct clk_hw *[]) {
    - &meson8b_hdmi_pll_dco.hw
    + &meson8b_hdmi_pll_lvds_out.hw
    },
    .num_parents = 1,
    .flags = CLK_SET_RATE_PARENT,
    --
    2.25.1
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