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    Subject[PATCH AUTOSEL 5.4 257/266] drm/sun4i: hdmi ddc clk: Fix size of m divider
    Date
    From: Jernej Skrabec <jernej.skrabec@siol.net>

    [ Upstream commit 54e1e06bcf1cf6e7ac3f86daa5f7454add24b494 ]

    m divider in DDC clock register is 4 bits wide. Fix that.

    Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
    Reviewed-by: Chen-Yu Tsai <wens@csie.org>
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200413095457.1176754-1-jernej.skrabec@siol.net
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/sun4i/sun4i_hdmi.h | 2 +-
    drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
    2 files changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
    index 7ad3f06c127e..00ca35f07ba5 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
    +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
    @@ -148,7 +148,7 @@
    #define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3

    #define SUN4I_HDMI_DDC_CLK_REG 0x528
    -#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
    +#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3)
    #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)

    #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
    diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
    index 2ff780114106..12430b9d4e93 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
    +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
    @@ -33,7 +33,7 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
    unsigned long best_rate = 0;
    u8 best_m = 0, best_n = 0, _m, _n;

    - for (_m = 0; _m < 8; _m++) {
    + for (_m = 0; _m < 16; _m++) {
    for (_n = 0; _n < 8; _n++) {
    unsigned long tmp_rate;

    --
    2.25.1
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