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    Subject[PATCH v4 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL
    Date
    For iommu offset=0x48 register, only the previous mt8173/mt8183 use the
    name STANDARD_AXI_MODE, all the latest SoC extend the register more
    feature by different bits, for example: axi_mode, in_order_en, coherent_en
    and so on. So rename REG_MMU_MISC_CTRL may be more proper.

    This patch only rename the register name, no functional change.

    Signed-off-by: Chao Hao <chao.hao@mediatek.com>
    Reviewed-by: Yong Wu <yong.wu@mediatek.com>
    ---
    drivers/iommu/mtk_iommu.c | 14 +++++++-------
    drivers/iommu/mtk_iommu.h | 2 +-
    2 files changed, 8 insertions(+), 8 deletions(-)

    diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
    index 2be96f1cdbd2..88d3df5b91c2 100644
    --- a/drivers/iommu/mtk_iommu.c
    +++ b/drivers/iommu/mtk_iommu.c
    @@ -41,7 +41,7 @@
    #define F_INVLD_EN0 BIT(0)
    #define F_INVLD_EN1 BIT(1)

    -#define REG_MMU_STANDARD_AXI_MODE 0x048
    +#define REG_MMU_MISC_CTRL 0x048
    #define REG_MMU_DCM_DIS 0x050

    #define REG_MMU_CTRL_REG 0x110
    @@ -573,8 +573,10 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
    }
    writel_relaxed(0, data->base + REG_MMU_DCM_DIS);

    - if (data->plat_data->reset_axi)
    - writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
    + if (data->plat_data->reset_axi) {
    + /* The register is called STANDARD_AXI_MODE in this case */
    + writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
    + }

    if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
    dev_name(data->dev), (void *)data)) {
    @@ -718,8 +720,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
    struct mtk_iommu_suspend_reg *reg = &data->reg;
    void __iomem *base = data->base;

    - reg->standard_axi_mode = readl_relaxed(base +
    - REG_MMU_STANDARD_AXI_MODE);
    + reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
    reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
    reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
    reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
    @@ -743,8 +744,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
    dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
    return ret;
    }
    - writel_relaxed(reg->standard_axi_mode,
    - base + REG_MMU_STANDARD_AXI_MODE);
    + writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
    writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
    writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
    writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
    diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
    index ea949a324e33..1b6ea839b92c 100644
    --- a/drivers/iommu/mtk_iommu.h
    +++ b/drivers/iommu/mtk_iommu.h
    @@ -18,7 +18,7 @@
    #include <soc/mediatek/smi.h>

    struct mtk_iommu_suspend_reg {
    - u32 standard_axi_mode;
    + u32 misc_ctrl;
    u32 dcm_dis;
    u32 ctrl_reg;
    u32 int_control0;
    --
    2.18.0
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