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SubjectRe: [PATCH v5 00/11] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account
On Tue, Jun 16, 2020 at 10:02:42PM +0530, Vinod Koul wrote:
> Hi Serge,
>
> On 02-06-20, 12:27, Serge Semin wrote:
> > Vinod, Viresh
> >
> > Andy's finished his review. So all the patches of the series (except one rather
> > decorative, which we have different opinion of) are tagged by him. Since merge
> > window is about to be opened please consider to merge the series in. I'll really
> > need it to be in the kernel to provide the noLLP-problem fix for the Dw APB SSI
> > in 5.8.
>
> Sorry it was too late for 5.8.. merge window is closed now, i will
> review it shortly

Yeah, alas It's too late now. On the other hand this is probably for better since
I've discovered that the noLLP-related problem is more complicated than I thought
in the first place. Yes, the interrupt handling latency will cause the problem
with Rx FIFO overflow, but the overflow might still happen due to several other
reasons (mostly due to our APB bus being too slow, but it can still be partly
fixed, and I am looking for a convenient solution at the moment). So could you
please merge the series in without the next patches:
[PATCH v5 04/11] dmaengine: Introduce max SG list entries capability
[PATCH v5 11/11] dmaengine: dw: Initialize max_sg_nents capability
If I manage to fix the problem in general then I'll send another series with
those two patches being part of it. Otherwise they won't be much useful for my
platform. Sorry for inconvenience and thanks for understanding.

-Sergey

>
> --
> ~Vinod

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