Messages in this thread Patch in this message | | | From | Greentime Hu <> | Subject | [PATCH 07/13] riscv: Add has_vector/riscv_vsize to save vector features. | Date | Fri, 12 Jun 2020 15:09:56 +0800 |
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This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system.
[guoren@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> --- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c8527d770c98..9b02d8b069e3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif void riscv_fill_hwcap(void) { @@ -73,4 +77,12 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.27.0
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