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    Subject[PATCH 4.9 31/61] ARM: dts: imx: Correct B850v3 clock assignment
    Date
    From: Martyn Welch <martyn.welch@collabora.co.uk>

    [ Upstream commit 1d0c7bb20c083a6e810d2142545b5606f8131080 ]

    The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m
    to avoid stepping on the LVDS output's toes, as the PLL can't be clocked
    to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the
    same time.

    As we are using ipu1_di0 and ipu2_di0, ensure both are switched to
    to pll2_pfd2_396m to avoid issues. The LDB driver will switch the
    required IPU to ldb_di1 when it uses it to drive LVDS.

    Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
    Signed-off-by: Romain Perier <romain.perier@collabora.com>
    Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm/boot/dts/imx6q-b850v3.dts | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
    index 167f7446722a..e5e9a16155d9 100644
    --- a/arch/arm/boot/dts/imx6q-b850v3.dts
    +++ b/arch/arm/boot/dts/imx6q-b850v3.dts
    @@ -57,7 +57,7 @@
    assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
    <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
    <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
    - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
    + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
    assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
    <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
    <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
    --
    2.25.1


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