Messages in this thread | | | Subject | Re: [PATCH RFCv2 9/9] arm64: Support async page fault | From | Paolo Bonzini <> | Date | Mon, 1 Jun 2020 11:21:41 +0200 |
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On 31/05/20 14:44, Marc Zyngier wrote: >> >> Is there an ARM-approved way to reuse the S2 fault syndromes to detect >> async page faults? > > It would mean being able to set an ESR_EL2 register value into ESR_EL1, > and there is nothing in the architecture that would allow that,
I understand that this is not what you want to do and I'm not proposing it, but I want to understand this better: _in practice_ do CPUs check closely what is written in ESR_EL1?
In any case, the only way to implement this, it seems to me, would be a completely paravirtualized exception vector that doesn't use ESR at all.
On the other hand, for the page ready (interrupt) side assigning a PPI seems complicated but doable.
Paolo
> with > the exception of nested virt: a VHE guest hypervisor running at EL1 > must be able to observe S2 faults for its own S2, as synthesized by > the host hypervisor.
> The trouble is that: > - there is so far no commercially available CPU supporting NV > - even if you could get hold of such a machine, there is no > guarantee that such "EL2 syndrome at EL1" is valid outside of > the nested context > - this doesn't solve the issue for non-NV CPUs anyway
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