Messages in this thread | | | From | Guo Ren <> | Date | Mon, 1 Jun 2020 17:13:46 +0800 | Subject | Re: [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features. |
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Since it has been redesigned with new version spec, please change the first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu <greentime.hu@sifive.com> wrote: > > From: Guo Ren <guoren@linux.alibaba.com> > > This patch is used to detect vector support status of CPU and use > riscv_vsize to save the size of all the vector registers. It assumes > all harts has the same capabilities in SMP system. > > [greentime.hu@sifive.com: add support for dynamic vlen] > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > --- > arch/riscv/kernel/cpufeature.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c8527d770c98..5a68a926da68 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly; > #ifdef CONFIG_FPU > bool has_fpu __read_mostly; > #endif > +#ifdef CONFIG_VECTOR > +bool has_vector __read_mostly; > +unsigned long riscv_vsize __read_mostly; > +#endif > > void riscv_fill_hwcap(void) > { > @@ -73,4 +77,11 @@ void riscv_fill_hwcap(void) > if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > has_fpu = true; > #endif > + > +#ifdef CONFIG_VECTOR > + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { > + has_vector = true; > + riscv_vsize = csr_read(CSR_VLENB) * 32; > + } > +#endif > } > -- > 2.26.2 > >
-- Best Regards Guo Ren
ML: https://lore.kernel.org/linux-csky/
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