Messages in this thread | | | Date | Sat, 9 May 2020 13:33:07 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86: Use INVPCID mnemonic in invpcid.h |
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On Fri, May 08, 2020 at 11:22:47AM +0200, Uros Bizjak wrote: > Current minimum required version of binutils is 2.23, > which supports INVPCID instruction mnemonic. > > Replace the byte-wise specification of INVPCID with > this proper mnemonic. > > Signed-off-by: Uros Bizjak <ubizjak@gmail.com> > CC: "H. Peter Anvin" <hpa@zytor.com> > CC: Ingo Molnar <mingo@redhat.com> > CC: Thomas Gleixner <tglx@linutronix.de> > --- > arch/x86/include/asm/invpcid.h | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/asm/invpcid.h b/arch/x86/include/asm/invpcid.h > index 989cfa86de85..23749bbca0ad 100644 > --- a/arch/x86/include/asm/invpcid.h > +++ b/arch/x86/include/asm/invpcid.h > @@ -12,12 +12,9 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr, > * stale TLB entries and, especially if we're flushing global > * mappings, we don't want the compiler to reorder any subsequent > * memory accesses before the TLB flush. > - * > - * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and > - * invpcid (%rcx), %rax in long mode. > */ > - asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" > - : : "m" (desc), "a" (type), "c" (&desc) : "memory"); > + asm volatile ("invpcid %1, %0" > + : : "r" (type), "m" (desc) : "memory");
How about I make it even more readable when applying?
asm volatile("invpcid %[desc], %[type]" :: [desc] "m" (desc), [type] "r" (type) : "memory");
:-)
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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