Messages in this thread | | | Date | Thu, 7 May 2020 07:28:31 +0200 | From | Boris Brezillon <> | Subject | Re: [PATCH v5 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC |
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On Thu, 7 May 2020 08:15:37 +0800 "Ramuthevar,Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> + reg = readl(ebu_host->ebu + EBU_ADDR_SEL(ebu_host->cs_num)); > + writel(reg | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN, > + ebu_host->ebu + EBU_ADDR_SEL(ebu_host->cs_num));
Seriously, did you really think I would not notice what you're doing here? You're reading the previous value which either contains a default mapping or has the mapping set by the bootloader, and write it back to the register along with a new mask and the REGEN bit set (which BTW is wrong since you don't mask out other fields before updating them). This confirms that this Core -> FPI address translation exists and has to be set properly, so please stop lying about that.
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