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    Subject[PATCH v2 9/9] ARM: dts: r8a7742: Add GPIO nodes
    Date
    Describe GPIO blocks in the R8A7742 device tree.

    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
    Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    ---
    v1->v2:
    * Included the nodes in sort order
    ---

    arch/arm/boot/dts/r8a7742.dtsi | 90 ++++++++++++++++++++++++++++++++++
    1 file changed, 90 insertions(+)

    diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
    index 439ff24e7b3a..305d8086a3dd 100644
    --- a/arch/arm/boot/dts/r8a7742.dtsi
    +++ b/arch/arm/boot/dts/r8a7742.dtsi
    @@ -200,6 +200,96 @@
    #size-cells = <2>;
    ranges;

    + gpio0: gpio@e6050000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6050000 0 0x50>;
    + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 0 32>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 912>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 912>;
    + };
    +
    + gpio1: gpio@e6051000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6051000 0 0x50>;
    + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 32 30>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 911>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 911>;
    + };
    +
    + gpio2: gpio@e6052000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6052000 0 0x50>;
    + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 64 30>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 910>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 910>;
    + };
    +
    + gpio3: gpio@e6053000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6053000 0 0x50>;
    + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 96 32>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 909>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 909>;
    + };
    +
    + gpio4: gpio@e6054000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6054000 0 0x50>;
    + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 128 32>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 908>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 908>;
    + };
    +
    + gpio5: gpio@e6055000 {
    + compatible = "renesas,gpio-r8a7742",
    + "renesas,rcar-gen2-gpio";
    + reg = <0 0xe6055000 0 0x50>;
    + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
    + #gpio-cells = <2>;
    + gpio-controller;
    + gpio-ranges = <&pfc 0 160 32>;
    + #interrupt-cells = <2>;
    + interrupt-controller;
    + clocks = <&cpg CPG_MOD 907>;
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 907>;
    + };
    +
    pfc: pin-controller@e6060000 {
    compatible = "renesas,pfc-r8a7742";
    reg = <0 0xe6060000 0 0x250>;
    --
    2.17.1
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