lkml.org 
[lkml]   [2020]   [May]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
On Sat, May 02, 2020 at 07:03:57PM +0530, Anshuman Khandual wrote:
> Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX,
> SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 8 ++++++++
> arch/arm64/kernel/cpufeature.c | 13 +++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index f9e3b9350540..0f34927f52b9 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -790,6 +790,14 @@
> #define ID_ISAR6_DP_SHIFT 4
> #define ID_ISAR6_JSCVT_SHIFT 0
>
> +#define ID_MMFR4_EVT_SHIFT 28
> +#define ID_MMFR4_CCIDX_SHIFT 24
> +#define ID_MMFR4_LSM_SHIFT 20
> +#define ID_MMFR4_HPDS_SHIFT 16
> +#define ID_MMFR4_CNP_SHIFT 12
> +#define ID_MMFR4_XNX_SHIFT 8

Why didn't you add ID_MMFR4_AC2_SHIFT as well?

Will

\
 
 \ /
  Last update: 2020-05-05 13:15    [W:0.582 / U:0.072 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site