Messages in this thread | | | Date | Tue, 5 May 2020 12:12:41 +0100 | From | Will Deacon <> | Subject | Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register |
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On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > This adds basic building blocks required for ID_PFR2 CPU register which > provides information about the AArch32 programmers model which must be > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > per ARM DDI 0487F.a specification. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Mark Rutland <mark.rutland@arm.com> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index b4a40535a3d8..464e828a994d 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > u32 reg_id_mmfr3; > u32 reg_id_pfr0; > u32 reg_id_pfr1; > + u32 reg_id_pfr2; > > u32 reg_mvfr0; > u32 reg_mvfr1; > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e5317a6367b6..c977449e02db 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -153,6 +153,7 @@ > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
nit: but please group these defines by name rather than encoding.
Will
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