Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Mon, 4 May 2020 15:01:25 +0200 | Subject | Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM |
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Hi Prabhakar,
On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for iWave RZ/G1H Qseven System On Module. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Thanks for your patch!
> --- /dev/null > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi > @@ -0,0 +1,53 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the iWave RZ/G1H Qseven SOM > + * > + * Copyright (C) 2020 Renesas Electronics Corp. > + */ > + > +#include "r8a7742.dtsi" > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + compatible = "iwave,g21m", "renesas,r8a7742"; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x40000000>; > + }; > + > + memory@200000000 { > + device_type = "memory"; > + reg = <2 0x00000000 0 0x20000000>;
According to the schematics, the second bank is also 1 GiB, so the reg length should be 0x40000000.
> + };
> +&pfc { > + mmc1_pins: mmc1 { > + groups = "mmc1_data4", "mmc1_ctrl"; > + function = "mmc1"; > + }; > +}; > + > +&mmcif1 { > + pinctrl-0 = <&mmc1_pins>; > + pinctrl-names = "default"; > + > + vmmc-supply = <®_3p3v>; > + bus-width = <4>; > + non-removable; > + status = "okay"; > +};
The eMMC has an 8-bit data path. Is there any specific reason you use bus-width = <4>, and the "mmc1_data4" pin group?
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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