Messages in this thread | | | From | Andy Shevchenko <> | Date | Fri, 29 May 2020 17:03:39 +0300 | Subject | Re: [PATCH v5 2/4] SFH: PCI driver to add support of AMD sensor fusion Hub using HID framework |
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On Fri, May 29, 2020 at 4:42 PM Sandeep Singh <Sandeep.Singh@amd.com> wrote: > > From: Sandeep Singh <sandeep.singh@amd.com> > > AMD SFH uses HID over PCIe bus.SFH fw is part of MP2 > processor (MP2 which is an ARM® Cortex-M4 core based > co-processor to x86) and it runs on MP2 where in driver resides > on X86. This part of module will communicate with MP2 FW and > provide that data into DRAM > > Signed-off-by: Sandeep Singh <sandeep.singh@amd.com>
> Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Why you are submitting code if Nehal's SoB last in the list?
...
> Reported-by: kbuild test robot <lkp@intel.com>
I guess it's not applicable here, since it's a new code. Rather you may mentioned this in changelog in cover letter.
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> + write64(0x0, privdata->mmio + AMD_C2P_MSG2);
Hmm... What's write64()? Isn't it writeq()?
...
> + if (ACEL_EN & activestatus) { > + sensor_id[num_of_sensors] = ACCEL_IDX; > + num_of_sensors++; > + }
You can drop a lot of LOCs by doing
if (ACEL_EN & activestatus) sensor_id[num_of_sensors++] = ACCEL_IDX;
...
> + rc = pcim_iomap_regions(pdev, BIT(2), DRIVER_NAME); > + if (rc)
> + goto err_pci_enable;
Due to use of PCI managed functions error path is not needed at all. Return directly.
...
> + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); > + if (rc) { > + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); > + if (rc) > + goto err_dma_mask; > + }
rc = ...; if (rc) rc = ...; if (rc) return rc;
...
> +err_dma_mask: > + pci_clear_master(pdev);
PCI managed handling does it for you.
> +err_pci_enable: > + pci_set_drvdata(pdev, NULL);
Driver code does this for you.
> + return rc;
...
> + dev_info(&pdev->dev, "MP2 device found [%04x:%04x] (rev %x)\n", > + pdev->vendor, pdev->device, pdev->revision);
How is it useful? PCI core prints a lot of information which you may find in dmesg.
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> + privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL); > + if (!privdata)
> + rc = -ENOMEM;
How this has been tested?
> + privdata->pdev = pdev;
> + rc = amd_mp2_pci_init(privdata, pdev); > + if (rc) > + return rc; > + return 0;
return amd_mp2_pci_init(...);
...
> +static void amd_mp2_pci_remove(struct pci_dev *pdev) > +{ > + struct amd_mp2_dev *privdata = pci_get_drvdata(pdev); > + > + amd_stop_all_sensors(privdata->pdev);
> + pci_clear_master(pdev); > + pci_set_drvdata(pdev, NULL);
Same comments as per error path in the ->probe()
> +}
...
> +static const struct pci_device_id amd_mp2_pci_tbl[] = { > + {PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2)},
Spaces, please, { PCI...() },
> + {0}
0 is not needed here.
> +};
...
> +#ifndef PCIE_MP2_AMD_H > +#define PCIE_MP2_AMD_H
+ empty line
> +#include <linux/io-64-nonatomic-lo-hi.h> > +#include <linux/pci.h> > +#include <linux/types.h>
> +#define PCI_DEVICE_ID_AMD_MP2 0x15E4
Why not in the C file?
> +/* MP2 C2P Message Registers */ > +#define AMD_C2P_MSG0 0x10500 > +#define AMD_C2P_MSG1 0x10504 > +#define AMD_C2P_MSG2 0x10508 > +#define AMD_C2P_MSG3 0x1050c > +#define AMD_C2P_MSG4 0x10510 > +#define AMD_C2P_MSG5 0x10514 > +#define AMD_C2P_MSG6 0x10518 > +#define AMD_C2P_MSG7 0x1051c > +#define AMD_C2P_MSG8 0x10520 > +#define AMD_C2P_MSG9 0x10524 > + > +/* MP2 P2C Message Registers */ > +#define AMD_P2C_MSG0 0x10680 /*Do not use*/ > +#define AMD_P2C_MSG1 0x10684 > +#define AMD_P2C_MSG2 0x10688 > +#define AMD_P2C_MSG3 0x1068C /*MP2 debug info*/ > +#define AMD_P2C_MSG_INTEN 0x10690 /*MP2 int gen register*/ > +#define AMD_P2C_MSG_INTSTS 0x10694 /*Interrupt sts*/
Do you need all these in the header?
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> +#define write64 lo_hi_writeq > +#define read64 lo_hi_readq
Why?! You have writeq() definition or use lo_hi_*() directly.
...
> +int amd_mp2_get_sensor_num(struct pci_dev *dev, u8 *sensor_id);
+ blank line
> +#endif
-- With Best Regards, Andy Shevchenko
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