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    SubjectRe: [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing
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    Quoting Eugeniy Paltsev (2020-03-11 06:41:14)
    > Support setting PLL to bypass mode to support output frequency
    > equal to input one.
    >
    > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
    > ---

    Applied to clk-next

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