Messages in this thread | | | Subject | Re: [PATCH v3 01/13] clk: mmp: frac: Do not lose last 4 digits of precision | From | Stephen Boyd <> | Date | Wed, 27 May 2020 18:01:01 -0700 |
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Quoting Lubomir Rintel (2020-05-19 15:41:39) > While calculating the output rate of a fractional divider clock, the > value is divided and multipled by 10000, discarding the least > significant digits -- presumably to fit the intermediate value within 32 > bits. > > The precision we're losing is, however, not insignificant for things like > I2S clock. Maybe also elsewhere, now that since commit ea56ad60260e ("clk: > mmp2: Stop pretending PLL outputs are constant") the parent rates are more > precise and no longer rounded to 10000s. > > Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> > ---
Applied to clk-next
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