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    Subject[PATCH v3 0/6] arm64: tlb: add support for TTL feature
    Date
    In order to reduce the cost of TLB invalidation, ARMv8.4 provides
    the TTL field in TLBI instruction. The TTL field indicates the
    level of page table walk holding the leaf entry for the address
    being invalidated. This series provide support for this feature.

    When ARMv8.4-TTL is implemented, the operand for TLBIs looks like
    below:

    * +----------+-------+----------------------+
    * | ASID | TTL | BADDR |
    * +----------+-------+----------------------+
    * |63 48|47 44|43 0|


    This version updates some codes implementation according to Peter's
    suggestion, and adds some commit msg.

    See patches for details, Thanks.

    --
    ChangeList:
    v3:
    minor changes: reduce the indentation levels of __tlbi_level().

    v2:
    rebase series on Linux 5.7-rc1 and simplify the code implementation.

    v1:
    add support for TTL feature in arm64.


    Marc Zyngier (2):
    arm64: Detect the ARMv8.4 TTL feature
    arm64: Add level-hinted TLB invalidation helper

    Peter Zijlstra (Intel) (1):
    tlb: mmu_gather: add tlb_flush_*_range APIs

    Zhenyu Ye (3):
    arm64: Add tlbi_user_level TLB invalidation helper
    mm: tlb: Provide flush_*_tlb_range wrappers
    arm64: tlb: Set the TTL field in flush_tlb_range

    arch/arm64/include/asm/cpucaps.h | 3 +-
    arch/arm64/include/asm/sysreg.h | 1 +
    arch/arm64/include/asm/tlb.h | 29 +++++++++++++++-
    arch/arm64/include/asm/tlbflush.h | 49 +++++++++++++++++++++++----
    arch/arm64/kernel/cpufeature.c | 11 +++++++
    include/asm-generic/pgtable.h | 12 +++++--
    include/asm-generic/tlb.h | 55 ++++++++++++++++++++++---------
    mm/pgtable-generic.c | 22 +++++++++++++
    8 files changed, 157 insertions(+), 25 deletions(-)

    --
    2.19.1


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