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    SubjectRe: [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes
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    On 05/21/2020 08:49 PM, Will Deacon wrote:
    > On Tue, 19 May 2020 15:10:37 +0530, Anshuman Khandual wrote:
    >> This series is primarily motivated from an adhoc list from Mark Rutland
    >> during our previous ID_ISAR6 discussion [1]. The current proposal also
    >> accommodates some more suggestions from Will and Suzuki.
    >>
    >> This series adds missing 32 bit system registers (ID_PFR2, ID_DFR1 and
    >> ID_MMFR5), adds missing features bits on all existing system registers
    >> (32 and 64 bit) and some other miscellaneous changes. While here it also
    >> includes a patch which does macro replacement for various open bits shift
    >> encodings for various CPU ID registers. There is a slight re-order of the
    >> patches here as compared to the previous version (V1).
    >>
    >> [...]
    >
    > Applied to arm64 (for-next/cpufeature), thanks!
    >
    > [01/17] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
    > https://git.kernel.org/arm64/c/2a5bc6c47bc3
    > [02/17] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
    > https://git.kernel.org/arm64/c/1ed1b90a0594
    > [03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0
    > https://git.kernel.org/arm64/c/e965bcb06256
    > [04/17] arm64/cpufeature: Introduce ID_PFR2 CPU register
    > https://git.kernel.org/arm64/c/16824085a7dd
    > [05/17] arm64/cpufeature: Introduce ID_DFR1 CPU register
    > https://git.kernel.org/arm64/c/dd35ec070457
    > [06/17] arm64/cpufeature: Introduce ID_MMFR5 CPU register
    > https://git.kernel.org/arm64/c/152accf8476f
    > [07/17] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register
    > https://git.kernel.org/arm64/c/0ae43a99fe91
    > [08/17] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
    > https://git.kernel.org/arm64/c/fcd6535322cc
    > [09/17] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register
    > https://git.kernel.org/arm64/c/7cd51a5a84d1
    > [10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register
    > https://git.kernel.org/arm64/c/011e5f5bf529
    > [11/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register
    > https://git.kernel.org/arm64/c/14e270fa5c4c
    > [12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register
    > (no commit info)
    > [13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
    > (no commit info)
    > [14/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register
    > (no commit info)
    > [15/17] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register
    > (no commit info)
    > [16/17] arm64/cpufeature: Replace all open bits shift encodings with macros
    > (no commit info)
    > [17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
    > https://git.kernel.org/arm64/c/858b8a8039d0
    >
    > Note that Suzuki had comments on 12-16, so assume you'll respin those (I fixed
    > up the trivial comments on earlier patches myself).
    [PATCH 15/17] might need some more investigation and rework. Hence planning to
    defer that for later and respin the remaining patches (12, 13, 14, 16) for now.

    - Anshuman

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