Messages in this thread | | | Subject | Re: [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register | From | Anshuman Khandual <> | Date | Sun, 24 May 2020 06:39:33 +0530 |
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On 05/19/2020 07:14 PM, Suzuki K Poulose wrote: > On 05/19/2020 10:40 AM, Anshuman Khandual wrote: >> Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as >> per ARM DDI 0487F.a specification. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> >> Suggested-by: Will Deacon <will@kernel.org> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 4 ++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 95fdfc5e9bd0..f9dd2c5ab074 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -734,6 +734,10 @@ >> #endif >> /* id_aa64mmfr1 */ >> +#define ID_AA64MMFR1_ETS_SHIFT 36 >> +#define ID_AA64MMFR1_TWED_SHIFT 32 >> +#define ID_AA64MMFR1_XNX_SHIFT 28 >> +#define ID_AA64MMFR1_SPECSEI_SHIFT 24 >> #define ID_AA64MMFR1_PAN_SHIFT 20 >> #define ID_AA64MMFR1_LOR_SHIFT 16 >> #define ID_AA64MMFR1_HPD_SHIFT 12 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 7ce19f97ba73..1f10ff7df705 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -299,6 +299,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { >> }; >> static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), > > SpecSEI must be HIGHER_SAFE, like we did for MMFR4 ?
Sure, will change.
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