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    Subject[PATCH v5 4/5] arm64: tegra: Add DT node for T194 SMMU
    Date
    Add DT node for T194 SMMU to enable SMMU support.

    Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
    ---
    arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77 ++++++++++++++++++++++++
    1 file changed, 77 insertions(+)

    diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    index f4ede86e32b4..f7c4399afb55 100644
    --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    @@ -1620,6 +1620,83 @@ pcie@141a0000 {
    0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
    };

    + smmu: iommu@12000000 {
    + compatible = "arm,mmu-500","nvidia,tegra194-smmu-500";
    + reg = <0 0x12000000 0 0x800000>,
    + <0 0x11000000 0 0x800000>,
    + <0 0x10000000 0 0x800000>;
    + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
    + stream-match-mask = <0x7f80>;
    + #global-interrupts = <3>;
    + #iommu-cells = <1>;
    + };
    +
    pcie_ep@14160000 {
    compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
    power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
    --
    2.26.2
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