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    SubjectRe: [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled
    On Wed, May 20, 2020 at 03:38:27PM +0200, Thomas Bogendoerfer wrote:
    > On Wed, May 20, 2020 at 03:12:01PM +0300, Serge Semin wrote:
    > > Since you don't like the way I initially fixed it, suppose there we don't have
    > > another way but to introduce something like CONFIG_MIPS_CPS_NS16550_WIDTH
    > > parameter to select a proper accessors, like sw in our case, and sb by defaul).
    > > Right?
    >
    > to be on the safe side it's probably the best thing. But I don't know
    > enough about CPS_NS16550 to judge whether shift value correlates with
    > possible access width.

    The base address passed to the _mips_cps_putc() leaf is UART-base address. It
    has nothing to do with CPS. See:
    /**
    * _mips_cps_putc() - write a character to the UART
    * @a0: ASCII character to write
    * @t9: UART base address
    */
    LEAF(_mips_cps_putc)
    1: lw t0, UART_LSR_OFS(t9)
    andi t0, t0, UART_LSR_TEMT
    beqz t0, 1b
    sb a0, UART_TX_OFS(t9)
    jr ra
    END(_mips_cps_putc)

    So it's base address must be accessed with proper alignment. On our case it's
    lw/sw instructions. Regarding using lw in the first line of the function. That's
    must be a bug, since further in the same function they use sb to access the UART
    Tx register. So reading a data from UART_LSR register should be also byte-sized
    by using lb.

    -Sergey

    >
    > Thomas.
    >
    > --
    > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
    > good idea. [ RFC1925, 2.3 ]

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