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SubjectRe: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port
On Thu, May 07, 2020 at 05:28:35PM +0530, Bharat Kumar Gogada wrote:
> Add YAML schemas documentation for Versal CPM Root Port driver.
>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 105 +++++++++++++++++++++
> 1 file changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> new file mode 100644
> index 0000000..5fc5c3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CPM Host Controller device tree for Xilinx Versal SoCs
> +
> +maintainers:
> + - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> +

allOf:
- $ref: /schemas/pci/pci-bus.yaml#

> +properties:
> + compatible:
> + const: xlnx,versal-cpm-host-1.00
> +

> + "#address-cells":
> + const: 3
> +
> + "#size-cells":
> + const: 2

Can drop.

> +
> + reg:
> + items:
> + - description: Configuration space region and bridge registers.
> + - description: CPM system level control and status registers.
> +
> + reg-names:
> + items:
> + - const: cfg
> + - const: cpm_slcr
> +
> + interrupts:
> + maxItems: 1
> +
> + msi-map:
> + description:
> + Maps a Requester ID to an MSI controller and associated MSI sideband data.
> +
> + ranges:
> + maxItems: 2
> +
> + "#interrupt-cells":
> + const: 1
> +

> + interrupt-map-mask:
> + description: Standard PCI IRQ mapping properties.
> +
> + interrupt-map:
> + description: Standard PCI IRQ mapping properties.

Can drop these 2.

> +
> + interrupt_controller:

s/_/-/

> + description: Interrupt controller child node.

type: object

And then need to describe all the properties under it too.

> +
> + bus-range:
> + description: Range of bus numbers associated with this controller.

Can drop.

> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
> + - reg
> + - reg-names
> + - "#interrupt-cells"
> + - interrupts
> + - interrupt-parent
> + - interrupt-map
> + - interrupt-map-mask
> + - ranges
> + - bus-range
> + - msi-map

interrupt-controller node not required?

You can drop all the standard properties required in pci-bus.yaml (it's
in dtschema repo).

> +
> +additionalProperties: false

This will need to be 'unevaluatedProperties: false'

> +
> +examples:
> + - |
> +
> + versal {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + cpm_pcie: pci@fca10000 {

pcie@...

> + compatible = "xlnx,versal-cpm-host-1.00";
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + interrupts = <0 72 4>;
> + interrupt-parent = <&gic>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
> + <0 0 0 2 &pcie_intc_0 1>,
> + <0 0 0 3 &pcie_intc_0 2>,
> + <0 0 0 4 &pcie_intc_0 3>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
> + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
> + msi-map = <0x0 &its_gic 0x0 0x10000>;
> + reg = <0x6 0x00000000 0x0 0x10000000>,
> + <0x0 0xfca10000 0x0 0x1000>;
> + reg-names = "cfg", "cpm_slcr";
> + pcie_intc_0: interrupt_controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller ;
> + };
> + };
> + };
> --
> 2.7.4
>

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