Messages in this thread | | | Date | Wed, 20 May 2020 15:34:34 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup |
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On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote: > Cadence driver uses "mem" memory resource to obtain the offset of > configuration space address region, memory space address region and > message space address region. The obtained offset is used to program > the Address Translation Unit (ATU). However certain platforms like TI's > J721E SoC require the absolute address to be programmed in the ATU and not > just the offset.
Once again, Cadence host binding is broken (or at least the example is). The 'mem' region shouldn't even exist. It is overlapping the config space and 'ranges':
reg = <0x0 0xfb000000 0x0 0x01000000>, <0x0 0x41000000 0x0 0x00001000>, <0x0 0x40000000 0x0 0x04000000>; reg-names = "reg", "cfg", "mem";
ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
16M of registers looks a bit odd. I guess it doesn't matter unless you have a 32-bit platform and care about your virtual space. Probably should have been 3 regions for LM, RP, and AT looking at the driver.
Whatever outbound address translation you need should be based on 'ranges'.
Rob
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