lkml.org 
[lkml]   [2020]   [May]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
    Date
    Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as
    per ARM DDI 0487F.a specification.

    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org

    Suggested-by: Will Deacon <will@kernel.org>
    Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
    ---
    arch/arm64/include/asm/sysreg.h | 4 ++++
    arch/arm64/kernel/cpufeature.c | 4 ++++
    2 files changed, 8 insertions(+)

    diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
    index fdf782de6723..ede03da1cf59 100644
    --- a/arch/arm64/include/asm/sysreg.h
    +++ b/arch/arm64/include/asm/sysreg.h
    @@ -730,6 +730,10 @@
    #endif

    /* id_aa64mmfr1 */
    +#define ID_AA64MMFR1_ETS_SHIFT 36
    +#define ID_AA64MMFR1_TWED_SHIFT 32
    +#define ID_AA64MMFR1_XNX_SHIFT 28
    +#define ID_AA64MMFR1_SPECSEI_SHIFT 24
    #define ID_AA64MMFR1_PAN_SHIFT 20
    #define ID_AA64MMFR1_LOR_SHIFT 16
    #define ID_AA64MMFR1_HPD_SHIFT 12
    diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
    index 0286319d9b08..005bc5ce3926 100644
    --- a/arch/arm64/kernel/cpufeature.c
    +++ b/arch/arm64/kernel/cpufeature.c
    @@ -296,6 +296,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
    };

    static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
    --
    2.20.1
    \
     
     \ /
      Last update: 2020-05-02 15:36    [W:4.272 / U:0.748 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site