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    Subject[PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs.
    Date
    Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi
    and x1000.dtsi files.

    Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
    Tested-by: Paul Boddie <paul@boddie.org.uk>
    Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
    ---

    Notes:
    v1->v2:
    No change.

    v2->v3:
    No change.

    v3->v4:
    Rebase on top of kernel 5.6-rc1.

    v4->v5:
    No change.

    v5->v6:
    No change.

    v6->v7:
    Update compatible strings.

    v7->v8:
    No change.

    arch/mips/boot/dts/ingenic/jz4740.dtsi | 14 ++++++++++++++
    arch/mips/boot/dts/ingenic/jz4770.dtsi | 15 ++++++++++++++-
    arch/mips/boot/dts/ingenic/jz4780.dtsi | 23 +++++++++++++++++++++++
    arch/mips/boot/dts/ingenic/x1000.dtsi | 14 ++++++++++++++
    4 files changed, 65 insertions(+), 1 deletion(-)

    diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
    index a3301ba..1f2f896 100644
    --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
    +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
    @@ -7,6 +7,20 @@
    #size-cells = <1>;
    compatible = "ingenic,jz4740";

    + cpus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + device_type = "cpu";
    + compatible = "ingenic,xburst-mxu1.0";
    + reg = <0>;
    +
    + clocks = <&cgu JZ4740_CLK_CCLK>;
    + clock-names = "cpu";
    + };
    + };
    +
    cpuintc: interrupt-controller {
    #address-cells = <0>;
    #interrupt-cells = <1>;
    diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
    index 0bfb9ed..12c7101 100644
    --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
    +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
    @@ -1,5 +1,4 @@
    // SPDX-License-Identifier: GPL-2.0
    -
    #include <dt-bindings/clock/jz4770-cgu.h>

    / {
    @@ -7,6 +6,20 @@
    #size-cells = <1>;
    compatible = "ingenic,jz4770";

    + cpus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + device_type = "cpu";
    + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
    + reg = <0>;
    +
    + clocks = <&cgu JZ4770_CLK_CCLK>;
    + clock-names = "cpu";
    + };
    + };
    +
    cpuintc: interrupt-controller {
    #address-cells = <0>;
    #interrupt-cells = <1>;
    diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
    index bb89653..03aeeff 100644
    --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
    +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
    @@ -8,6 +8,29 @@
    #size-cells = <1>;
    compatible = "ingenic,jz4780";

    + cpus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + device_type = "cpu";
    + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
    + reg = <0>;
    +
    + clocks = <&cgu JZ4780_CLK_CPU>;
    + clock-names = "cpu";
    + };
    +
    + cpu1: cpu@1 {
    + device_type = "cpu";
    + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
    + reg = <1>;
    +
    + clocks = <&cgu JZ4780_CLK_CORE1>;
    + clock-names = "cpu";
    + };
    + };
    +
    cpuintc: interrupt-controller {
    #address-cells = <0>;
    #interrupt-cells = <1>;
    diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
    index 147f7d5..2205e1b 100644
    --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
    +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
    @@ -8,6 +8,20 @@
    #size-cells = <1>;
    compatible = "ingenic,x1000", "ingenic,x1000e";

    + cpus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + device_type = "cpu";
    + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
    + reg = <0>;
    +
    + clocks = <&cgu X1000_CLK_CPU>;
    + clock-names = "cpu";
    + };
    + };
    +
    cpuintc: interrupt-controller {
    #address-cells = <0>;
    #interrupt-cells = <1>;
    --
    2.7.4
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