Messages in this thread | | | From | Kevin Hilman <> | Subject | Re: [PATCH 0/2] ARM: dts: meson8b/m2: RGMII improvements | Date | Tue, 19 May 2020 17:07:46 -0700 |
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On Tue, 12 May 2020 23:51:46 +0200, Martin Blumenstingl wrote: > the fist patch in this series connects FCLK_DIV2 to the PRG_ETH > "additional" registers for the dwmac Ethernet controller. > Now that we know how RGMII and FCLK_DIV2 are connected we can > add this dependency to get rid of CLK_IS_CRITICAL for FCLK_DIV2 > at some point. > > The second patch fixes the RX and TX delay. The 4ns TX delay which > we have used so far is incorrect and only worked because we were > using an unsupported clock divider in the PRG_ETH registers. That > divider has been fixed with commit bd6f48546b9c ("net: stmmac: > dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). > Instead of "just" fixing the TX delay we can even do better and > switch to phy-mode = "rgmii-id" to let the PHY generate the RX > and TX delay. However, previously we didn't know that there was > an RX delay applied by the MAC on these boards. Only the additional > information from Jianxin in the other series [0] made us aware > of this. Without the other series there will be a 4ns RX delay > (2ns from the MAC and additional 2ns from the PHY). Due to this > dependency I did not add a Fixes tag, because backporting these > .dts patches without their runtime dependency will break stable > kernels. > > [...]
Applied, thanks!
[1/2] ARM: dts: meson: Add the Ethernet "timing-adjustment" clock commit: b632506c5af22a9a7c63674fc605d24cf94d585b [2/2] ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" commit: 005231128e9e97461e81fa32421957a7664317ca
Best regards, -- Kevin Hilman <khilman@baylibre.com>
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