Messages in this thread | | | Subject | RE: [PATCH V4 2/4] x86/resctrl: Enumerate per-thread MBA | From | Babu Moger <> | Date | Mon, 18 May 2020 12:29:40 -0500 |
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> -----Original Message----- > From: Reinette Chatre <reinette.chatre@intel.com> > Sent: Saturday, May 16, 2020 1:29 PM > To: tglx@linutronix.de; fenghua.yu@intel.com; bp@alien8.de; > tony.luck@intel.com > Cc: kuo-lang.tseng@intel.com; ravi.v.shankar@intel.com; mingo@redhat.com; > Moger, Babu <Babu.Moger@amd.com>; hpa@zytor.com; x86@kernel.org; > linux-kernel@vger.kernel.org; Reinette Chatre <reinette.chatre@intel.com> > Subject: [PATCH V4 2/4] x86/resctrl: Enumerate per-thread MBA > > From: Fenghua Yu <fenghua.yu@intel.com> > > Some systems support per-thread Memory Bandwidth Allocation (MBA) which > applies a throttling delay value to each hardware thread instead of to > a core. Per-thread MBA is enumerated by CPUID. > > No feature flag is shown in /proc/cpuinfo. User applications need to > check a resctrl throttling mode info file to know if the feature is > supported. > > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> > Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
> --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/cpuid-deps.c | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index db189945e9b0..d0ec26ce7f66 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -286,6 +286,7 @@ > #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user > entry SWAPGS path */ > #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" > LFENCE in kernel entry SWAPGS path */ > #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock > */ > +#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread > Memory Bandwidth Allocation */ > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 > BFLOAT16 instructions */ > diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid- > deps.c > index 3cbe24ca80ab..3e30b26c50ef 100644 > --- a/arch/x86/kernel/cpu/cpuid-deps.c > +++ b/arch/x86/kernel/cpu/cpuid-deps.c > @@ -69,6 +69,7 @@ static const struct cpuid_dep cpuid_deps[] = { > { X86_FEATURE_CQM_MBM_TOTAL, > X86_FEATURE_CQM_LLC }, > { X86_FEATURE_CQM_MBM_LOCAL, > X86_FEATURE_CQM_LLC }, > { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, > + { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA > }, > {} > }; > > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 62b137c3c97a..bccfc9ff3cc1 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -35,6 +35,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 > }, > { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 > }, > { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 }, > + { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 > }, > { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, > { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > -- > 2.21.0
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