Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH v12 00/18] Enable FSGSBASE instructions | Date | Tue, 19 May 2020 01:03:25 +0200 |
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Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> writes: > On Mon, 2020-05-18 at 08:34 -0700, Andi Kleen wrote: >> > Yes, for SGX this is functional feature because enclave entry points, >> > thread control structures (aka TCS's), reset FSBASE and GSBASE registers >> > to fixed (albeit user defined) values. And syscall's can be done only >> > outside of enclave. >> > >> > This is a required feature for fancier runtimes (such as Graphene). >> >> Can you please explain a bit more? What do they need GS for? > > Apparently, uses only wrfsbase: > > https://raw.githubusercontent.com/oscarlab/graphene/master/Pal/src/host/Linux-SGX/db_misc.c > > I'm not too familiar with the codebase yet but by reading some research > papers in the past the idea is to multiplex one TCS for multiple virtual > threads inside the enclave. > > E.g. TCS could represent a vcpu for a libos type of container and on > entry would pick on a thread and set fsbase accordingly for a thread > control block.
That justifies to write books which recommend to load a kernel module which creates a full unpriviledged root hole. I bet none of these papers ever mentioned that.
Thanks,
tglx
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