Messages in this thread | | | Subject | Re: [PATCH v1 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180 | From | Taniya Das <> | Date | Sun, 17 May 2020 14:50:41 +0530 |
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Hello Rob,
Thanks for the review.
On 4/5/2020 7:39 AM, Rob Herring wrote:
>> + >> + reg: >> + minItems: 1 >> + maxItems: 2 > > Need to define what each one is when there are 2. >
Yes will define them in the next patch.
>> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - '#power-domain-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> >> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> >> + clock-controller@63000000 { >> + compatible = "qcom,sc7180-lpasshm"; >> + reg = <0 0x63000000 0 0x28>; >> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; >> + clock-names = "gcc_lpass_sway"; >> + #clock-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + - | >> + clock-controller@62d00000 { >> + compatible = "qcom,sc7180-lpasscorecc"; >> + reg = <0 0x62d00000 0 0x50000>, >> + <0 0x62780000 0 0x30000>; >> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; >> + clock-names = "gcc_lpass_sway"; >> + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; >> + #clock-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> +...
> /* GCC resets */ >> #define GCC_QUSB2PHY_PRIM_BCR 0 >> diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> new file mode 100644 >> index 0000000..9466d5e >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> @@ -0,0 +1,28 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright (c) 2020, The Linux Foundation. All rights reserved. >> + */ >> + >> +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H >> +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H >> + >> +/* LPASS_CORE_CC clocks */ >> +#define LPASS_LPAAUDIO_DIG_PLL 0 >> +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 >> +#define CORE_CLK_SRC 2 >> +#define EXT_MCLK0_CLK_SRC 3 >> +#define LPAIF_PRI_CLK_SRC 4 >> +#define LPAIF_SEC_CLK_SRC 5 >> +#define LPASS_AUDIO_CORE_CORE_CLK 6 >> +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 >> +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 >> +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 >> +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 >> + >> +/* LPASS power domains */ >> +#define LPASS_CORE_HM_GDSCR 0 >> + >> +#define LPASS_AUDIO_HM_GDSCR 0 > > Kind of odd that 2 are the same value. >
These GDSCs are from two different domains. I will update the comments in the next patch.
>> +#define LPASS_PDC_HM_GDSCR 1 >> + >> +#endif >> -- >> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member >> of the Code Aurora Forum, hosted by the Linux Foundation. >>
-- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation.
--
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