Messages in this thread | | | Date | Sat, 16 May 2020 17:06:27 +0300 | From | Serge Semin <> | Subject | Re: [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode |
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On Fri, May 15, 2020 at 03:27:00PM +0300, Andy Shevchenko wrote: > On Fri, May 15, 2020 at 01:47:44PM +0300, Serge Semin wrote: > > It's pointless to track the Tx overrun interrupts if Rx-only SPI > > transfer is issued. Similarly there is no need in handling the Rx > > overrun/underrun interrupts if Tx-only SPI transfer is executed. > > So lets unmask the interrupts only if corresponding SPI > > transactions are implied. > > My comments below. > > > Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> > > Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > > Cc: Paul Burton <paulburton@kernel.org> > > Cc: Ralf Baechle <ralf@linux-mips.org> > > Cc: Arnd Bergmann <arnd@arndb.de> > > Cc: Allison Randal <allison@lohutok.net> > > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Cc: Gareth Williams <gareth.williams.jx@renesas.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: linux-mips@vger.kernel.org > > Cc: devicetree@vger.kernel.org > > I think you really need to revisit Cc list in all patches (DT people hardly > interested in this one, though ones where properties are being used might be > point of interest). > > ... > > > /* Set the interrupt mask */ > > - spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI); > > + spi_umask_intr(dws, imr); >
> Can we rather do like this > > /* Set the interrupt mask */ > if (xfer->tx_buf) > imr |= SPI_INT_TXOI; > if (xfer->rx_buf) > imr |= SPI_INT_RXUI | SPI_INT_RXOI; > spi_umask_intr(dws, imr); > > ? > > (First block sets DMA, second one IRQ)
I'd rather leave it as is.
-Sergey
> > -- > With Best Regards, > Andy Shevchenko > >
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