Messages in this thread | | | Subject | Re: [PATCH v6 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC | From | "Ramuthevar, Vadivel MuruganX" <> | Date | Fri, 15 May 2020 10:06:22 +0800 |
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Hi Rob,
Thank you for the review comments...
On 14/5/2020 9:03 pm, Rob Herring wrote: > On Wed, May 13, 2020 at 06:46:14PM +0800, Ramuthevar,Vadivel MuruganX wrote: >> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> >> Add YAML file for dt-bindings to support NAND Flash Controller >> on Intel's Lightning Mountain SoC. >> >> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> --- >> .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 83 ++++++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> >> diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> new file mode 100644 >> index 000000000000..d9e0df8553fa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: GPL-2.0 > > Dual license new bindings please: > > (GPL-2.0-only OR BSD-2-Clause) Noted. > >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Intel LGM SoC NAND Controller Device Tree Bindings >> + >> +allOf: >> + - $ref: "nand-controller.yaml" >> + >> +maintainers: >> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> + >> +properties: >> + compatible: >> + const: intel,lgm-nand-controller >> + >> + reg: >> + maxItems: 1 > > Looks like you have 4 or 6 entries, not 1. Need to define what each one > is. Sure, will define it. > >> + >> + clocks: >> + maxItems: 1 >> + >> + dmas: >> + maxItems: 2 >> + >> + dma-names: >> + enum: >> + - rx >> + - tx > > This defines a single entry. I believe you want: > > items: > - const: tx > - const: rx Yes, Thanks!
> >> + >> + pinctrl-names: true > > No need for this. Tools add pinctrl properties. will drop it. > >> + >> +patternProperties: >> + "^nand@[a-f0-9]+$": >> + type: object >> + properties: >> + reg: >> + minimum: 0 >> + maximum: 7 >> + >> + nand-ecc-mode: true >> + >> + nand-ecc-algo: >> + const: hw >> + >> + additionalProperties: false >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - dmas >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + nand-controller@e0f00000 { >> + compatible = "intel,nand-controller"; > > Doesn't match the schema. Noted, will update the schema name. > >> + reg = <0xe0f00000 0x100>, >> + <0xe1000000 0x300>, >> + <0xe1400000 0x8000>, >> + <0xe1c00000 0x1000>; > > Is it 4 or 6 entries? yes, will update. > >> + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", >> + "addr_sel0","addr_sel1"; > > Not documented. Noted, will document it. > >> + clocks = <&cgu0 125>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + #clock-cells = <1>; > > This is a clock provider too? Yes, it is getting clock from CGU for nand-controller.
Regards Vadivel > >> + >> + nand@0 { >> + reg = <0>; >> + nand-on-flash-bbt; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + }; >> + }; >> + >> +... >> -- >> 2.11.0 >>
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