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    Subject[PATCH 5.4 35/83] PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports
    Date
    From: Raymond Pang <RaymondPang-oc@zhaoxin.com>

    commit 299bd044a6f332b4a6c8f708575c27cad70a35c1 upstream.

    Many Zhaoxin Root Ports and Switch Downstream Ports do provide ACS-like
    capability but have no ACS Capability Structure. Peer-to-Peer transactions
    could be blocked between these ports, so add quirk so devices behind them
    could be assigned to different IOMMU group.

    Link: https://lore.kernel.org/r/20200327091148.5190-4-RaymondPang-oc@zhaoxin.com
    Signed-off-by: Raymond Pang <RaymondPang-oc@zhaoxin.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/pci/quirks.c | 25 +++++++++++++++++++++++++
    1 file changed, 25 insertions(+)

    --- a/drivers/pci/quirks.c
    +++ b/drivers/pci/quirks.c
    @@ -4371,6 +4371,29 @@ static int pci_acs_ctrl_enabled(u16 acs_
    }

    /*
    + * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
    + * But the implementation could block peer-to-peer transactions between them
    + * and provide ACS-like functionality.
    + */
    +static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
    +{
    + if (!pci_is_pcie(dev) ||
    + ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
    + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
    + return -ENOTTY;
    +
    + switch (dev->device) {
    + case 0x0710 ... 0x071e:
    + case 0x0721:
    + case 0x0723 ... 0x0732:
    + return pci_acs_ctrl_enabled(acs_flags,
    + PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
    + }
    +
    + return false;
    +}
    +
    +/*
    * AMD has indicated that the devices below do not support peer-to-peer
    * in any system where they are found in the southbridge with an AMD
    * IOMMU in the system. Multifunction devices that do not support
    @@ -4772,6 +4795,8 @@ static const struct pci_dev_acs_enabled
    { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
    { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
    { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
    + /* Zhaoxin Root/Downstream Ports */
    + { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
    { 0 }
    };


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