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    Subject[PATCH 4.4 27/70] iio: xilinx-xadc: Fix clearing interrupt when enabling trigger
    Date
    From: Lars-Peter Clausen <lars@metafoo.de>

    commit f954b098fbac4d183219ce5b42d76d6df2aed50a upstream.

    When enabling the trigger and unmasking the end-of-sequence (EOS) interrupt
    the EOS interrupt should be cleared from the status register. Otherwise it
    is possible that it was still set from a previous capture. If that is the
    case the interrupt would fire immediately even though no conversion has
    been done yet and stale data is being read from the device.

    The old code only clears the interrupt if the interrupt was previously
    unmasked. Which does not make much sense since the interrupt is always
    masked at this point and in addition masking the interrupt does not clear
    the interrupt from the status register. So the clearing needs to be done
    unconditionally.

    Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
    Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver")
    Cc: <Stable@vger.kernel.org>
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/iio/adc/xilinx-xadc-core.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/iio/adc/xilinx-xadc-core.c
    +++ b/drivers/iio/adc/xilinx-xadc-core.c
    @@ -660,7 +660,7 @@ static int xadc_trigger_set_state(struct

    spin_lock_irqsave(&xadc->lock, flags);
    xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
    - xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS);
    + xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
    if (state)
    val |= XADC_AXI_INT_EOS;
    else

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