Messages in this thread | | | Subject | Re: [PATCH v3 3/6] bus: mhi: core: Offload register accesses to the controller | From | Hemant Kumar <> | Date | Tue, 28 Apr 2020 11:56:03 -0700 |
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On 4/27/20 8:59 AM, Jeffrey Hugo wrote: > When reading or writing MHI registers, the core assumes that the physical > link is a memory mapped PCI link. This assumption may not hold for all > MHI devices. The controller knows what is the physical link (ie PCI, I2C, > SPI, etc), and therefore knows the proper methods to access that link. > The controller can also handle link specific error scenarios, such as > reading -1 when the PCI link went down. > > Therefore, it is appropriate that the MHI core requests the controller to > make register accesses on behalf of the core, which abstracts the core > from link specifics, and end up removing an unnecessary assumption. > > Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> > --- Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
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