Messages in this thread | | | From | Peng Fan <> | Subject | RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core | Date | Mon, 27 Apr 2020 08:58:49 +0000 |
| |
> Subject: RE: [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use > composite core > > > From: Peng Fan <peng.fan@nxp.com> > > Sent: Thursday, March 12, 2020 6:20 PM > > > > Migrate A53 clk root to use composite core clk type. It will simplify > > code and make it easy to use composite specific mux operation. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > drivers/clk/imx/clk-imx8mm.c | 6 +++--- drivers/clk/imx/clk-imx8mn.c > > | 6 > > +++--- drivers/clk/imx/clk-imx8mq.c | 6 +++--- > > 3 files changed, 9 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/clk/imx/clk-imx8mm.c > > b/drivers/clk/imx/clk-imx8mm.c index > > 5435042a06e3..12443e06f329 100644 > > --- a/drivers/clk/imx/clk-imx8mm.c > > +++ b/drivers/clk/imx/clk-imx8mm.c > > @@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct > > platform_device *pdev) > > return PTR_ERR(base); > > > > /* Core Slice */ > > - hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", > base + > > 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); > > - hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", > > "arm_a53_src", base + 0x8000, 28); > > - hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", > > "arm_a53_cg", base + 0x8000, 0, 3); > > + hws[IMX8MM_CLK_A53_DIV] = > > imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + > > 0x8000); > > + hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV]; > > + hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV]; > > The former patch already breaks the compatibility. > Not sure if we really need keep it for only A53 clock here as we are still at > very early enablement Phase for MX8MP. So we may just remove them > IMHO.
i.MX8MM, not i.MX8MP.
Thanks, Peng.
> Shawn, what's your suggestion? > > Regards > Aisheng > > > > > hws[IMX8MM_CLK_M4_CORE] = > > imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + > > 0x8080); > > hws[IMX8MM_CLK_VPU_CORE] = > > imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + > > 0x8100); diff --git a/drivers/clk/imx/clk-imx8mn.c > > b/drivers/clk/imx/clk-imx8mn.c index 6cac6ca03e12..bd3759b4afd0 > 100644 > > --- a/drivers/clk/imx/clk-imx8mn.c > > +++ b/drivers/clk/imx/clk-imx8mn.c > > @@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct > > platform_device > > *pdev) > > } > > > > /* CORE */ > > - hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base > + > > 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)); > > - hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", > > "arm_a53_src", base + 0x8000, 28); > > - hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", > > "arm_a53_cg", base + 0x8000, 0, 3); > > + hws[IMX8MN_CLK_A53_DIV] = > > imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + > > 0x8000); > > + hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; > > + hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; > > > > hws[IMX8MN_CLK_GPU_CORE] = > > imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base > + > > 0x8180); > > hws[IMX8MN_CLK_GPU_SHADER] = > > imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, > base > > + 0x8200); diff --git a/drivers/clk/imx/clk-imx8mq.c > > b/drivers/clk/imx/clk-imx8mq.c index 201c7bbb201f..91309ff65441 100644 > > --- a/drivers/clk/imx/clk-imx8mq.c > > +++ b/drivers/clk/imx/clk-imx8mq.c > > @@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct > > platform_device > > *pdev) > > return PTR_ERR(base); > > > > /* CORE */ > > - hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base > + > > 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)); > > - hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", > > "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL); > > - hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", > > "arm_a53_cg", base + 0x8000, 0, 3); > > + hws[IMX8MQ_CLK_A53_DIV] = > > imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + > > 0x8000); > > + hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; > > + hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; > > > > hws[IMX8MQ_CLK_M4_CORE] = > > imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, > base > > + 0x8080); > > hws[IMX8MQ_CLK_VPU_CORE] = > > imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + > > 0x8100); > > -- > > 2.16.4
| |