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    Subject[tip: x86/mm] x86/mm: Move pgprot2cachemode out of line
    The following commit has been merged into the x86/mm branch of tip:

    Commit-ID: 7fa3e10f0f3646108a1018004d0f571c3222dc9f
    Gitweb: https://git.kernel.org/tip/7fa3e10f0f3646108a1018004d0f571c3222dc9f
    Author: Christoph Hellwig <hch@lst.de>
    AuthorDate: Wed, 08 Apr 2020 17:27:43 +02:00
    Committer: Borislav Petkov <bp@suse.de>
    CommitterDate: Mon, 20 Apr 2020 12:39:17 +02:00

    x86/mm: Move pgprot2cachemode out of line

    This helper is only used by x86 low-level MM code. Also remove the
    entirely pointless __pte2cachemode_tbl export as that symbol can be
    marked static now.

    Signed-off-by: Christoph Hellwig <hch@lst.de>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/20200408152745.1565832-3-hch@lst.de
    ---
    arch/x86/include/asm/memtype.h | 1 +
    arch/x86/include/asm/pgtable_types.h | 10 ----------
    arch/x86/mm/init.c | 13 +++++++++++--
    3 files changed, 12 insertions(+), 12 deletions(-)

    diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h
    index 1e4e99b..9ca760e 100644
    --- a/arch/x86/include/asm/memtype.h
    +++ b/arch/x86/include/asm/memtype.h
    @@ -25,5 +25,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end);
    extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn);

    bool x86_has_pat_wp(void);
    +enum page_cache_mode pgprot2cachemode(pgprot_t pgprot);

    #endif /* _ASM_X86_MEMTYPE_H */
    diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
    index b6606fe..75fe903 100644
    --- a/arch/x86/include/asm/pgtable_types.h
    +++ b/arch/x86/include/asm/pgtable_types.h
    @@ -468,7 +468,6 @@ static inline pteval_t pte_flags(pte_t pte)
    }

    extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
    -extern uint8_t __pte2cachemode_tbl[8];

    #define __pte2cm_idx(cb) \
    ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
    @@ -489,15 +488,6 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
    {
    return __pgprot(cachemode2protval(pcm));
    }
    -static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
    -{
    - unsigned long masked;
    -
    - masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
    - if (likely(masked == 0))
    - return 0;
    - return __pte2cachemode_tbl[__pte2cm_idx(masked)];
    -}
    static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
    {
    pgprotval_t val = pgprot_val(pgprot);
    diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
    index 6005f83..4a55d68 100644
    --- a/arch/x86/mm/init.c
    +++ b/arch/x86/mm/init.c
    @@ -59,7 +59,7 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
    };
    EXPORT_SYMBOL(__cachemode2pte_tbl);

    -uint8_t __pte2cachemode_tbl[8] = {
    +static uint8_t __pte2cachemode_tbl[8] = {
    [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
    [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
    [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
    @@ -69,7 +69,6 @@ uint8_t __pte2cachemode_tbl[8] = {
    [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
    [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
    };
    -EXPORT_SYMBOL(__pte2cachemode_tbl);

    /* Check that the write-protect PAT entry is set for write-protect */
    bool x86_has_pat_wp(void)
    @@ -77,6 +76,16 @@ bool x86_has_pat_wp(void)
    return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
    }

    +enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
    +{
    + unsigned long masked;
    +
    + masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
    + if (likely(masked == 0))
    + return 0;
    + return __pte2cachemode_tbl[__pte2cm_idx(masked)];
    +}
    +
    static unsigned long __initdata pgt_buf_start;
    static unsigned long __initdata pgt_buf_end;
    static unsigned long __initdata pgt_buf_top;
    \
     
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