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Subject[PATCH 2/2] devicetree: bindings: phy: Document dwc3 qcom phy
Date
Document dwc3 qcom phy hs and ss phy bindings needed to correctly
inizialize and use usb on ipq806x SoC

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/phy/qcom,dwc3-hs-usb-phy.yaml | 65 +++++++++++++++++++
.../bindings/phy/qcom,dwc3-ss-usb-phy.yaml | 65 +++++++++++++++++++
2 files changed, 130 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml
new file mode 100644
index 000000000000..0bb59e3c2ab8
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dwc3-hs-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm DWC3 HS PHY CONTROLLER
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description:
+ DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+ controllers. Each DWC3 PHY controller should have its own node.
+
+properties:
+ compatible:
+ const: qcom,dwc3-hs-usb-phy
+
+ "#phy-cells":
+ const: 0
+
+ regmap:
+ maxItems: 1
+ description: phandle to usb3 dts definition
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ description: |
+ - "ref" Is required
+ - "xo" Optional external reference clock
+ items:
+ - const: ref
+ - const: xo
+
+required:
+ - compatible
+ - "#phy-cells"
+ - regmap
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+ hs_phy_0: hs_phy_0 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ regmap = <&usb3_0>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_0: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ reg = <0x110f8800 0x8000>;
+
+ /* ... */
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml
new file mode 100644
index 000000000000..2f7b0d9db072
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dwc3-ss-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm DWC3 SS PHY CONTROLLER
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description:
+ DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+ controllers. Each DWC3 PHY controller should have its own node.
+
+properties:
+ compatible:
+ const: qcom,dwc3-ss-usb-phy
+
+ "#phy-cells":
+ const: 0
+
+ regmap:
+ maxItems: 1
+ description: phandle to usb3 dts definition
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ description: |
+ - "ref" Is required
+ - "xo" Optional external reference clock
+ items:
+ - const: ref
+ - const: xo
+
+required:
+ - compatible
+ - "#phy-cells"
+ - regmap
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+ ss_phy_0: ss_phy_0 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ regmap = <&usb3_0>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_0: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ reg = <0x110f8800 0x8000>;
+
+ /* ... */
+ };
--
2.25.1
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