Messages in this thread | | | Subject | Re: [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] | From | Suzuki K Poulose <> | Date | Fri, 17 Apr 2020 10:37:50 +0100 |
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On 04/15/2020 01:29 PM, Will Deacon wrote: > On Wed, Apr 15, 2020 at 12:37:31PM +0100, Suzuki K Poulose wrote: >> On 04/15/2020 11:58 AM, Will Deacon wrote: >>> On Wed, Apr 15, 2020 at 11:50:58AM +0100, Suzuki K Poulose wrote: >>>> On 04/14/2020 10:31 PM, Will Deacon wrote: >>>>> We don't need to be quite as strict about mismatched AArch32 support, >>>>> which is good because the friendly hardware folks have been busy >>>>> mismatching this to their hearts' content. >>>>> >>>>> * We don't care about EL2 or EL3 (there are silly comments concerning >>>>> the latter, so remove those) >>>>> >>>>> * EL1 support is gated by the ARM64_HAS_32BIT_EL1 capability and handled >>>>> gracefully when a mismatch occurs >>>>> >>>>> * EL1 support is gated by the ARM64_HAS_32BIT_EL0 capability and handled >>>> >>>> s/EL1/EL0 >>>> >>>>> gracefully when a mismatch occurs >>>>> >>>>> Relax the AArch32 checks to FTR_NONSTRICT. >>>> >>>> Agreed. We should do something similar for the features exposed by the >>>> ELF_HWCAP, of course in a separate series. >>> >>> Hmm, I didn't think we needed to touch the HWCAPs, as they're derived from >>> the sanitised feature register values. What am I missing? >> >> sorry, that was cryptic. I was suggesting to relax the ftr fields to >> NONSTRICT for the fields covered by ELF HWCAPs (and other CPU hwcaps). > > Ah, gotcha. Given that the HWCAPs usually describe EL0 features, I say we > can punt this down the road until people give us hardware with mismatched > AArch32 at EL0.
Btw, this is not just mismatched AArch32, but mismatched AArch64 HWCAPs too, which I believe exists. Anyways as you said, we can delay this until we get the reports :-)
Suzuki
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